INTRODUCTION

BACKGROUND

The source of supply for global chip makers mainly comes from the two giants ARM and Intel, which also makes more and more companies began to worry, in case one day the two hegemony to raise the price of their products or cut off the supply chain, where do we go from here, just at this time, the idea of joining forces to establish a completely open-source new architecture was born in some of the enterprise.

RISCV is an open source Instruction Set Architecture (ISA) based on the principles of Reduced Instruction Set Computing (RISC), supporting free and open RISC instruction set architectures and extensions.

MOTIVATION & GOALS

This work explores and implements a three stage pipeline for RISCV core based on PFGA and simulates RAM, ROM and other peripherals.

METHOD

This work references the work of tinyriscv, an excellent open source project design by Kangnan Liang.

Figure 1. Overall Architecture of Openriscv.

MATERIALS

Photo taken in Duisburg, Germany in 2021, board model PYNQ Z1, courtesy of Zhengzhou University IoT Innovation Lab.

EXPERIMENT

Figure 1. PYNQ Z1.